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RT8015B 1 ds8015b-04 march 2011 www.richtek.com features z z z z z high efficiency : up to 95% z z z z z low r ds(on) internal switches : 110m z z z z z programmable frequency : 300khz to 2mhz z z z z z no schottky diode required z z z z z 0.8v reference allows for low output voltage z z z z z forced continuous mode operation z z z z z low dropout operation : 100% duty cycle z z z z z power good output voltage indicator z z z z z rohs compliant and halogen free applications z portable instruments z battery-powered equipment z notebook computers z distributed power systems z ip phones z digital cameras general description the RT8015B is a high efficiency synchronous, step down dc/dc converter. its input voltage range is from 2.6v to 5.5v and provides an adjustable regulated output voltage from 0.8v to 5v while delivering up to 3a of output current. the internal synchronous low on resistance power switches increase efficiency and eliminate the need for an external schottky diode. the switching frequency is set by an external resistor. the 100% duty cycle provides low dropout operation extending battery life in portable systems. current mode operation with external compensation allows the transient response to be optimized over a wide range of loads and output capacitors. the RT8015B is operated in forced continuous pwm mode which minimizes ripple voltage and reduces the noise and rf interference. the 100% duty cycle in low dropout operation further maximize battery life. the RT8015B is available in the wdfn-10l 3x3 and sop- 8 (exposed pad) packages. ordering information pin configurations (top view) wdfn-10l 3x3 3a, 2mhz, synchronous step-down converter note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. shdn/rt gnd pgnd lx comp fb pgood pvdd vdd lx 9 8 7 9 1 2 3 4 5 10 11 shdn/rt gnd lx pgnd comp fb pvdd vdd 2 3 4 5 6 7 8 gnd 9 sop-8 (exposed pad) marking information for marking information, contact our sales representative directly or through a richtek distributor located in your area. RT8015B package type qw : wdfn-10l 3x3 sp : sop-8 (exposed pad-option 2) lead plating system g : green (halogen free and pb free)
RT8015B 2 ds8015b-04 march 2011 www.richtek.com functional pin description pin no. wdfn -10l 3x3 sop-8 (exposed pad) pin name pin function 1 1 shdn/rt oscillator resistor input. connecting a resistor to ground from this pin sets the switching frequency. forcing this pin to v dd causes the device to be shut down. 2 2 gnd signal ground. all small
RT8015B 3 ds8015b-04 march 2011 www.richtek.com function block diagram layout guide driver nisen control logic nmos i limit 0.9v 0.7v 0.2v oc limit isen slope com osc output clamp ea 0.8v int-ss por otp v ref comp shdn/rt gnd fb pvdd vdd pgnd sd lx pgood v in gnd l1 v out gnd c in c out v out c comp r2 r1 c f r osc place the input and output capacitors as close to the ic as possible. lx should be connected to inductor by wide and short trace, keep sensitive components away from this trace place the feedback and compensation components as close to the ic as possible. RT8015B shdn/rt gnd pgnd lx comp fb pgood vdd pvdd lx 4 3 2 6 7 8 9 10 5 1 r comp r4 r3 c1 gnd bottom layer
RT8015B 4 ds8015b-04 march 2011 www.richtek.com operation main control loop the RT8015B is a monolithic, constant-frequency, current mode step-down dc/dc converter. during normal operation, the internal top power switch (p-channel mosfet) is turned on at the beginning of each clock cycle. current in the inductor increases until the peak inductor current reach the value defined by the voltage on the comp pin. the error amplifier adjusts the voltage on the comp pin by comparing the feedback signal from a resistor divider on the fb pin with an internal 0.8v reference. when the load current increases, it causes a reduction in the feedback voltage relative to the reference. the error amplifier raises the comp voltage until the average inductor current matches the new load current. when the top power mosfet shuts off, the synchronous power switch (n-mosfet) turns on until either the bottom current limit is reached or the beginning of the next clock cycle. the operating frequency is set by an external resistor connected between the rt pin and ground. the practical switching frequency can range from 300khz to 2mhz. dropout operation when the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maximum on-time. further reduction of the supply voltage forces the main switch to remain on for more than one cycle eventually reaching 100% duty cycle. the output voltage will then be determined by the input voltage minus the voltage drop across the internal p-channel mosfet and the inductor. low supply operation the RT8015B is designed to operate down to an input supply voltage of 2.6v. one important consideration at low input supply voltages is that the r ds(on) of the p-channel and n-channel power switches increases. the user should calculate the power dissipation when the RT8015B is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. slope compensation and inductor peak current slope compensation provides stability in constant frequency architectures by preventing sub-harmonic oscillations at duty cycles greater than 50%. it is accomplished internally by adding a compensating ramp to the inductor current signal. normally, the maximum inductor peak current is reduced when slope compensation is added. in the RT8015B, however, separated inductor current signals are used to monitor over current condition. this keeps the maximum output current relatively constant regardless of duty cycle. short circuit protection when the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. a current runaway detector is used to monitor inductor current. as current increasing beyond the control of current loop, switching cycles will be skipped to prevent current runaway from occurring.
RT8015B 5 ds8015b-04 march 2011 www.richtek.com absolute maximum ratings (note 1) z supply input voltage, vdd, pvdd ---------------------------------------------------------------------------- ? 0.3v to 6v z lx pin switch voltage -------------------------------------------------------------------------------------------- ? 0.3v to (pvdd + 0.3v) <200ns --------------------------------------------------------------------------------------------------------------- ? 5v to 7.5v z other i/o pin v oltages ------------------------------------------------------------------------------------------- ? 0.3v to (vdd + 0.3v) z lx pin switch current -------------------------------------------------------------------------------------------- 4a z power dissipation, p d @ t a = 25 c sop-8 (exposed pad) ------------------------------------------------------------------------------------------- 1.333w wdf n-10l 3x3 ----------------------------------------------------------------------------------------------------- 1.429w z package thermal resistance (note 2) sop-8 (exposed pad), ja ------------------------------------------------------------------------------------- 75 c/w sop-8 (exposed pad), jc ------------------------------------------------------------------------------------- 15 c/w wdfn-10l 3x3, ja ----------------------------------------------------------------------------------------------- 70 c/w wdfn-10l 3x3, jc ----------------------------------------------------------------------------------------------- 8.2 c/w z junction temperature --------------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ---------------- ------------------------------------------------------- 260 c z storage temperature range ------------------------------------------------------------------------------------ ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) -------------------------------------------------------------------------------------- 2kv mm (ma chine mode) ---------------------------------------------------------------------------------------------- 200v electrical characteristics (v dd = 3.3v, t a = 25 c, unless otherwise specified) to be continued recommended operating conditions (note 4) z supply input voltage ---------------------------------------------------------------------------------------------- 2.6v to 5.5v z junction temperature range ------------------------------------------------------------------------------------ ? 40 c to 125 c z ambient temperature range ------------------------------------------------------------------------------------ ? 40 c to 85 c parameter symbol test conditions min typ max unit input voltage range v dd 2.6 -- 5.5 v feedback reference voltage v ref 0.784 0.8 0.816 v feedback leakage current i fb -- 0.1 0.4 ?
RT8015B 6 ds8015b-04 march 2011 www.richtek.com note 1. stresses listed as the above "absolute maximum ratings" may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in natural convection at t a = 25 c on a high-effective thermal conductivity four-layer test board of jedec 51-7 thermal measurement standard. the measurement case position of jc is on the exposed pad of the packages. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. the specifications over the -40 c to 85 c operation ambient temperature range are assured by design, characterization and correlation with statistical process controls. parameter symbol test conditions min typ max unit r osc = 332k 0.8 1 1.2 mhz switching frequency switching frequency 0.3 -- 2 mhz switch on resistance, high r pmos i sw = 0.5a -- 110 160 m ? ?
RT8015B 7 ds8015b-04 march 2011 www.richtek.com typical operating characteristics quiescent current vs. input voltage 360 370 380 390 400 410 420 430 440 450 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) quiescent current (ua) output voltage vs. load current 2.456 2.460 2.464 2.468 2.472 2.476 2.480 2.484 2.488 2.492 0.00.51.01.52.02.53.0 load current (a) output voltage (v) v in = 5v peak current limit vs. input voltage 2.0 2.5 3.0 3.5 4.0 4.5 5.0 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5 input voltage (v) current limit (a) v out = 2.5v frequency vs. temperature 0.98 1.00 1.02 1.04 1.06 1.08 -50 -25 0 25 50 75 100 125 temperature frequency (mhz) v in = 5v, v out = 2.5v, i out = 0a ( c) quiescent current vs. temperature 380 390 400 410 420 430 440 450 -50-25 0 25 50 75100125 temperature quiescent current (ua) v in = 5v ( c) efficiency vs. load current 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 load current (a) efficiency (%) v in = 5v v in = 5.5v v out = 2.5v v in = 4.5v
RT8015B 8 ds8015b-04 march 2011 www.richtek.com output voltage vs. temperature 3.22 3.24 3.26 3.28 3.30 3.32 3.34 -50 -25 0 25 50 75 100 125 temperature output voltage (v) v in = 5v ( c) uvp time (4 s/div) i lx (5a/div) v lx (5v/div) v in = 5v, v out = 1.05v v out (1v/div) pgood (5v/div) load transient response time (100 s/div) i load (1a/div) v out_ac (100mv/div) v in = 5v, v out = 2.5v i out = 0a to 3a output ripple time (400ns/div) i lx (2a/div) v lx (5v/div) v in = 5v, v out = 2.5v i out = 3a v out_ac (10mv/div) start up with no load time (400 s/div) v lx (5v/div) v in = 5v, v out = 10.5v, i out = 0a v out (1v/div) v in (5v/div) pgood (5v/div) start up with heavy load time (400 s/div) v in = 5v, v out = 1.05v, i out = 3a v lx (5v/div) v out (1v/div) v in (5v/div) pgood (5v/div)
RT8015B 9 ds8015b-04 march 2011 www.richtek.com application information the basic RT8015B application circuit is shown in typical application circuit. external component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by c in and c out . output voltage programming the output voltage is set by an external resistive divider according to the following equation : figure 1. setting the output voltage ? ? ? ? ? ? + = [ ) frequency (mhz) r osc (k ) rt = 152k for 2mhz rt = 330k for 1mhz RT8015B fb gnd v out r1 r2 where v ref equals to 0.8v typical. the resistive divider allows the fb pin to sense a fraction of the output voltage as shown in figure 1. time (1ms/div) i lx (1a/div) v out (500mv/div) v in (2v/div) v in = 5v, v out = 1.05v, i out = 2a
RT8015B 10 ds8015b-04 march 2011 www.richtek.com the output ripple is highest at maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr but can be used in cost sensitive 1 v v v v i i out in in out out(max) rms ? = ? ? ? ? ? ? + ? hard ? , which means that inductance collapses abruptly when the peak design current is exceeded. this result in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? ? =
RT8015B 11 ds8015b-04 march 2011 www.richtek.com applications provided that consideration is given to ripple current ratings and long term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load(esr) , where esr is the effective series resistance of c out . i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the comp pin external components and output capacitor shown in typical application circuit will provide adequate compensation for most applications. efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. efficiency can be expressed as : efficiency = 100% ? (l1+ l2+ l3+ ...) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: v dd quiescent current and i 2 r losses. the v dd quiescent current loss dominates the efficiency loss at very low load currents whereas the i 2 r loss dominates the efficiency loss at medium to high load currents. in a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence. 1. the v dd quiescent current is due to two components : the dc bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. the gate charge current results from switching the gate capacitance of the internal power mosfet switches. each time the gate is switched from high to low to high again, a packet of charge q moves from v dd to ground. the resulting q/ t is the current out of v dd that is typically larger than the dc bias current. in continuous mode, i gatechg = f(qt+qb) where qt and qb are the gate charges of the internal top and bottom switches. both the dc bias and gate charge losses are proportional to v dd and thus their effects will be more pronounced at higher supply voltages. 2. i 2 r losses are calculated from the resistances of the internal switches, rsw and external inductor rl. in continuous mode, the average output current flowing through inductor l is ? chopped ? between the main switch and the synchronous switch. thus, the series resistance looking into the lx pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (d) as follows : r sw = r ds(on) top x d + r ds(on) bot x (1"d) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus, to obtain i 2 r losses, simply add rsw to rl and multiply the result by the square of the average output current. other losses including c in and c out esr dissipative losses and inductor core losses generally account for less than 2% of the total loss.
RT8015B 12 ds8015b-04 march 2011 www.richtek.com layout considerations follow the pcb layout guidelines for optimal performance of RT8015B. ` a ground plane is recommended. if a ground plane layer is not used, the signal and power grounds should be segregated with all small-signal components returning to the gnd pin at one point that is then connected to the pgnd pin close to the ic. the exposed pad should be connected to gnd. ` connect the terminal of the input capacitor(s), c in , as close as possible to the pvdd pin. this capacitor provides the ac current into the internal power mosfets. ` lx node is with high frequency voltage swing and should be kept within small area. keep all sensitive small-signal nodes away from the lx node to prevent stray capacitive noise pick-up. ` flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of powercomponents. you can connect the copper areas to any dc net (pvdd, vdd, vout, pgnd, gnd, or any other dc rail in your system). current limit RT8015B has cycle by cycle current limiting control. the current limit circuit employs a ? peak ? current sensing algorithm. if the magnitude of the current sense signal is above the current limit threshold, the controller will turn off high side mosfet and turn on low side mosfet. under voltage protection (uvp) the output voltage can be continuously monitored for under voltage protection. when the output voltage is less than 25% of its set voltage threshold, the under voltage protection circuit will be triggered to terminate switching operation and the controller will be latched unless vdd por is detected again. during soft-start, the uvp will be blanked until soft-start finish. thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications of the RT8015B, the maximum junction temperature is 125 c and t a is the ambient temperature. the junction to ambient thermal resistance, ja , is layout dependent. for sop-8 (exposed pad) packages, the thermal resistance, ja , is 75 c/w on a standard jedec 51-7 four-layer thermal test board. for wdfn-10l 3x3 packages, the thermal resistance, ja , is 70 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formulas : p d(max) = (125 c ? 25 c) / (75 c/w) = 1.333w for sop-8 (exposed pad) package p d(max) = (125 c ? 25 c) / (70 c/w) = 1.429w for wdfn-10l 3x3 package figure 4. derating curves for RT8015B package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . for the RT8015B packages, the derating curves in figure 4 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) wdfn-10l 3x3 four-layer pcb sop-8 (exposed pad)
RT8015B 13 ds8015b-04 march 2011 www.richtek.com figure 5 figure 6 ` connect the fb pin directly to the feedback resistors. the resistor divider must be connected between v out and gnd.
RT8015B 14 ds8015b-04 march 2011 www.richtek.com component supplier series inductance ( h) dcr (m ) current rating (ma) dimensions (mm) taiyo yuden nr 8040 2 9 7800 8x8x4 table 1. inductors component supplier part no. capacitance ( f) case size tdk c3225x5r0j226m 22 1210 tdk c2012x5r0j106m 10 0805 panasonic ecj4yb0j226m 22 1210 panasonic ecj4yb1a106m 10 1210 taiyo yuden lmk325bj226ml 22 1210 taiyo yuden jmk316bj226ml 22 1206 taiyo yuden jmk212bj106ml 10 0805 table 2. capacitors for c in and c out recommended component selection for typical application
RT8015B 15 ds8015b-04 march 2011 www.richtek.com outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 2.950 3.050 0.116 0.120 d2 2.300 2.650 0.091 0.104 e 2.950 3.050 0.116 0.120 e2 1.500 1.750 0.059 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 10l dfn 3x3 package 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options d 1 e a3 a a1 d2 e2 l b e see detail a
RT8015B 16 ds8015b-04 march 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com a b j f h m c d i y x exposed thermal pad (bottom of package) 8-lead sop (exposed pad) plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 4.000 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.510 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.000 0.152 0.000 0.006 j 5.791 6.200 0.228 0.244 m 0.406 1.270 0.016 0.050 x 2.000 2.300 0.079 0.091 option 1 y 2.000 2.300 0.079 0.091 x 2.100 2.500 0.083 0.098 option 2 y 3.000 3.500 0.118 0.138

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